The present invention relates generally to the art of semiconductor devices and more particularly to improved NMOS devices with thin silicide for improved ESD protection in integrated circuit devices.
Electrostatic discharge (ESD) is a continuing problem in the design and manufacture of semiconductor devices. Integrated circuits (ICs) can be damaged by ESD events stemming from a variety of sources, in which large currents flow through the device. In one such ESD event, a packaged IC acquires a charge when it is held by a human whose body is electrostatically charged. An ESD event occurs when the IC is inserted into a socket, and one or more of the pins of the IC package touch the grounded contacts of the socket. This type of event is known as a human body model (HBM) ESD stress. For example, a charge of about 0.6 xcexcC can be induced on a body capacitance of 150 pF, leading to electrostatic potentials of 4 kV or greater. HBM ESD events can result in a discharge for about 100 nS with peak currents of several amperes to the IC. Another source of ESD is from metallic objects, known as the machine model (MM) ESD source, which is characterized by a greater capacitance and lower internal resistance than the HBM ESD source. The MM ESD model can result in ESD transients with significantly higher rise times than the HBM ESD source. A third ESD model is the charged device model (CDM), which involves situations where an IC becomes charged and discharges to ground. In this model, the ESD discharge current flows in the opposite direction in the IC than that of the HBM ESD source and the MM ESD source. CDM pulses also typically have very fast rise times compared to the HBM ESD source.
ESD events typically involve discharge of current between one or more pins or pads exposed to the outside of an integrated circuit chip. Such ESD current flows from the pad to ground through vulnerable circuitry in the IC, which may not be designed to carry such currents. Many ESD protection techniques have been thusfar employed to reduce or mitigate the adverse effects of ESD events in integrated circuit devices. Many conventional ESD protection schemes for ICs employ peripheral dedicated circuits to carry the ESD currents from the pin or pad of the device to ground by providing a low impedance path thereto. In this way, the ESD currents flow through the protection circuitry, rather than through the more susceptible circuits in the chip.
Such protection circuitry is typically connected to I/O and other pins or pads on the IC, wherein the pads further provide the normal circuit connections for which the IC was designed. Some ESD protection circuits carry ESD currents directly to ground, and others provide the ESD current to the supply rail of the IC for subsequent routing to ground. Rail-based clamping devices can be employed to provide a bypass path from the IC pad to the supply rail (e.g., VDD) of the device. Thereafter, circuitry associated with powering the chip is used to provide such ESD currents to the ground. Local clamps are more common, wherein the ESD currents are provided directly to ground from the pad or pin associated with the ESD event. Individual local clamps are typically provided at each pin on an IC, with the exception of the ground pin or pins.
One common technique for creating local clamping devices for protection of metal-oxide semiconductor (MOS) ICs is to create an N-channel MOS transistor device (NMOS), in which a parasitic bipolar transistor (e.g., a lateral NPN, or LNPN) associated with the NMOS clamp device turns on to conduct ESD currents from the pad to ground. The bipolar transistor is formed from the NMOS device, wherein the P-type doped channel between the drain and source acts as the NPN base, and the N-type drain and source act as the bipolar collector and emitter, respectively. Typically, the drain of the NMOS clamp is connected to the pad or pin to be protected and the source and gate are tied to ground. Current flowing through the substrate to ground creates a base to emitter voltage (Vbe) sufficient to turn on the bipolar device, whereby further ESD current flows from the drain (collector) at the pad to the grounded source (emitter).
The parasitic bipolar transistor (LNPN) operates in a snapback region when the ESD event brings the potential of the pad or pin positive with respect to ground. In order to provide effective ESD protection, it is desirable to provide an LNPN having a low trigger voltage to begin snapback operation, as well as a high ESD current capability within the snapback region. In practice, the LNPN enters the snapback region of operation upon reaching an initial trigger voltage Vt1 having a corresponding current It1. Thereafter, the LNPN conducts ESD current to ground to protect other circuitry in the IC, so long as the ESD current does not exceed a second breakdown current level It2 with a corresponding voltage Vt2. If the ESD stress currents exceed It2, thermal runaway is induced in the protective clamp device, wherein the reduction of the impact ionization current is offset by the thermal generation of carriers. This breakdown is initiated in a device under stress as a result of self-heating, and causes failure of the ESD clamping device, allowing ESD currents to damage other circuitry in the IC. To avoid such ESD clamp device failure and the associated IC damage, it is therefore desirable to provide LNPN clamping devices having high It2 breakdown current ratings.
Because the NMOS transistor and associated LNPN are designed for relatively large current conduction, such devices typically include multiple fingers for each of the drain, source, and gate. One problem with such multi-finger devices is found where Vt1 is greater than Vt2. In this situation, one finger of the device may turn on, causing operation of a portion of the device to operate in snapback mode. Thereafter, the remaining fingers may not reach Vt1 due to the snapback operation of the first finger. As a result, the full ESD current conduction capability for the LNPN is not utilized, and the current may exceed breakdown levels for the fingers operating in the snapback region, resulting in thermal device failure. Accordingly, it is desirable to provide multi-finger LNPNs having Vt2 greater than Vt1 to ensure all the fingers transition into the snapback region in a predictable fashion and thereby to avoid such unintended ESD protection device failure.
Many circuits have been proposed and implemented for protecting ICs from ESD. One method that is used to improve ESD protection for ICs is biasing the substrate of ESD protection circuits on an IC. Such substrate biasing can be effective at improving the response of a multi-finger NMOS transistor that is used to conduct an ESD discharge to ground. However, substrate biasing can cause the threshold voltages for devices to change from their nominal values, which may affect device operation. In addition, substrate biasing under steady-state conditions causes heat generation and increases power losses in the IC. Thus, although substrate biasing may increase the response of ESD protection of multi-finger MOS transistors, the additional problems caused by substrate biasing may limit its effectiveness or applicability. Thus, there remains a need for improved ESD clamping devices having high current capability for protecting ICs from damage or failure during ESD events, and which provide for increased It2 capacity.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to ESD protection circuitry and methods for making such. In particular NMOS transistors are provided having parasitic bipolar LNPNs associated therewith, for use in local or rail-based ESD clamping applications. It has been found that thinner silicide in the drain (e.g., and/or in the source) of the NMOS increases the It2 breakdown current level. The invention provides increased It2 current capabilities for such devices through selective employment of thin silicide in the drain and/or source regions of the NMOS transistor. In addition, the thin silicide provides adjustable drain and/or source resistance by which Vt2 can be made greater than Vt1. Thus, the invention can be employed to provide improved ESD current clamping capability, as well as improved reliability of multi-finger NMOS clamping devices.
One aspect of the invention provides an NMOS ESD clamping device for protecting an integrated circuit from an ESD event, with N-type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness, and a thin second silicide region is formed between the gate and the drain, and/or between the gate and the source. The second silicide is thinner than the first silicide, by which the It2 of the NMOS device can be increased. The selective application of the thin suicide improves (e.g., increases) It2 and/or allows relative adjustment of Vt1 and Vt2 in the ESD protection device, while allowing thicker silicide to be employed elsewhere in the IC. Thus, for example, the gate silicide in other devices in the IC can remain thick to achieve low gate resistance, while one or more silicide regions associated with the ESD protection devices can be made thinner.
The silicide thickness can be controlled using masking techniques, wherein polysilicon masks are formed around the regions where the thin suicide is desired. For example, polysilicon islands or dummy gates can be formed, which are narrowly spaced from the polysilicon gate fingers of the NMOS device. A silicide-forming metal, for example, such as cobalt, a silicide-forming metal, or nickel is then deposited, which is usually done via sputtering. The narrow spacings or gaps between the adjacent polysilicon regions results in reduction in the amount of silicide-forming metal deposition in the narrow gaps, due to the nature of the silicide-forming metal deposition. The reduction in the amount of silicide-forming metal in the narrow gaps, in turn, provides for thinner silicide in the gaps after subsequent reaction of the deposited metal with silicon to form silicide. Thus, the use of polysilicon masking can provide for selective formation of thin silicide for ESD clamping devices, while allowing a single metal deposition/reaction process to be employed throughout the IC, to provide thicker silicide in non-ESD related areas or regions of the device.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.